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404 lines
11 KiB
404 lines
11 KiB
/*
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* Copyright (C) 2006 iptelorg GmbH
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* @file
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* @brief Atomic ops and memory barriers for ARM (>= v3)
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*
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* Atomic ops and memory barriers for ARM architecture (starting from version 3)
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* see atomic_ops.h for more info.
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*
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* Config defines:
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* - NOSMP
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* - __CPU_arm
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* - __CPU_arm6 - armv6 support (supports atomic ops via ldrex/strex)
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* @ingroup atomic
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*/
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/*
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* History:
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* --------
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* 2006-03-31 created by andrei
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* 2007-05-10 added atomic_add and atomic_cmpxchg (andrei)
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* 2007-05-29 added membar_depends(), membar_*_atomic_op and
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* membar_*_atomic_setget (andrei)
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*/
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#ifndef _atomic_arm_h
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#define _atomic_arm_h
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#ifdef NOSMP
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#define HAVE_ASM_INLINE_MEMBAR
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#define membar() asm volatile ("" : : : "memory") /* gcc do not cache barrier*/
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#define membar_read() membar()
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#define membar_write() membar()
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#define membar_depends() do {} while(0) /* really empty, not even a cc bar.*/
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/* lock barriers: empty, not needed for NOSMP; the lock/unlock should already
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* contain gcc barriers*/
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#define membar_enter_lock() do {} while(0)
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#define membar_leave_lock() do {} while(0)
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/* membars after or before atomic_ops or atomic_setget -> use these or
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* mb_<atomic_op_name>() if you need a memory barrier in one of these
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* situations (on some archs where the atomic operations imply memory
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* barriers is better to use atomic_op_x(); membar_atomic_op() then
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* atomic_op_x(); membar()) */
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#define membar_atomic_op() membar()
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#define membar_atomic_setget() membar()
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#define membar_write_atomic_op() membar_write()
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#define membar_write_atomic_setget() membar_write()
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#define membar_read_atomic_op() membar_read()
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#define membar_read_atomic_setget() membar_read()
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#else /* SMP */
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#warning SMP not supported for arm atomic ops, try compiling with -DNOSMP
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/* fall back to default lock based barriers (don't define HAVE_ASM...) */
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#endif /* NOSMP */
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#ifdef __CPU_arm6
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#define HAVE_ASM_INLINE_ATOMIC_OPS
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/* hack to get some membars */
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#ifndef NOSMP
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#include "atomic_unknown.h"
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#endif
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/* main asm block
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* use %0 as input and write the output in %1*/
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#define ATOMIC_ASM_OP(op) \
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"1: ldrex %0, [%3] \n\t" \
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" " op "\n\t" \
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" strex %0, %1, [%3] \n\t" \
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" cmp %0, #0 \n\t" \
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" bne 1b \n\t"
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/* same as above but writes %4 instead of %1, and %0 will contain
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* the prev. val*/
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#define ATOMIC_ASM_OP2(op) \
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"1: ldrex %0, [%3] \n\t" \
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" " op "\n\t" \
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" strex %1, %4, [%3] \n\t" \
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" cmp %1, #0 \n\t" \
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" bne 1b \n\t"
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/* no extra param, %0 contains *var, %1 should contain the result */
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#define ATOMIC_FUNC_DECL(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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ATOMIC_ASM_OP(OP) \
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: "=&r"(tmp), "=&r"(ret), "=m"(*var) : "r"(var) : "cc" \
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); \
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return RET_EXPR; \
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}
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/* one extra param in %4 */
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#define ATOMIC_FUNC_DECL1(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE v) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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ATOMIC_ASM_OP(OP) \
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: "=&r"(tmp), "=&r"(ret), "=m"(*var) : "r"(var), "r"(v) : "cc" \
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); \
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return RET_EXPR; \
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}
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/* as above, but %4 should contain the result, and %0 is returned*/
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#define ATOMIC_FUNC_DECL2(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE v) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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ATOMIC_ASM_OP2(OP) \
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: "=&r"(ret), "=&r"(tmp), "=m"(*var) : "r"(var), "r"(v) : "cc" \
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); \
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return RET_EXPR; \
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}
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#define ATOMIC_XCHG_DECL(NAME, P_TYPE) \
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inline static P_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE v ) \
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{ \
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P_TYPE ret; \
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asm volatile( \
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" swp %0, %2, [%3] \n\t" \
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: "=&r"(ret), "=m"(*var) :\
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"r"(v), "r"(var) \
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); \
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return ret; \
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}
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/* cmpxchg: %5=old, %4=new_v, %3=var
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* if (*var==old) *var=new_v
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* returns the original *var (can be used to check if it succeeded:
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* if old==cmpxchg(var, old, new_v) -> success
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*/
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#define ATOMIC_CMPXCHG_DECL(NAME, P_TYPE) \
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inline static P_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE old, \
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P_TYPE new_v) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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"1: ldrex %0, [%3] \n\t" \
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" cmp %0, %5 \n\t" \
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" strexeq %1, %4, [%3] \n\t" \
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" cmp %1, #0 \n\t" \
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" bne 1b \n\t" \
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/* strexeq is exec. only if cmp was successful \
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* => if not successful %1 is not changed and remains 0 */ \
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: "=&r"(ret), "=&r"(tmp), "=m"(*var) :\
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"r"(var), "r"(new_v), "r"(old), "1"(0) : "cc" \
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); \
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return ret; \
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}
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ATOMIC_FUNC_DECL(inc, "add %1, %0, #1", int, void, /* no return */ )
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ATOMIC_FUNC_DECL(dec, "sub %1, %0, #1", int, void, /* no return */ )
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ATOMIC_FUNC_DECL1(and, "and %1, %0, %4", int, void, /* no return */ )
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ATOMIC_FUNC_DECL1(or, "orr %1, %0, %4", int, void, /* no return */ )
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ATOMIC_FUNC_DECL(inc_and_test, "add %1, %0, #1", int, int, ret==0 )
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ATOMIC_FUNC_DECL(dec_and_test, "sub %1, %0, #1", int, int, ret==0 )
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//ATOMIC_FUNC_DECL2(get_and_set, /* no extra op needed */ , int, int, ret)
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ATOMIC_XCHG_DECL(get_and_set, int)
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ATOMIC_CMPXCHG_DECL(cmpxchg, int)
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ATOMIC_FUNC_DECL1(add, "add %1, %0, %4", int, int, ret )
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ATOMIC_FUNC_DECL(inc, "add %1, %0, #1", long, void, /* no return */ )
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ATOMIC_FUNC_DECL(dec, "sub %1, %0, #1", long, void, /* no return */ )
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ATOMIC_FUNC_DECL1(and, "and %1, %0, %4", long, void, /* no return */ )
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ATOMIC_FUNC_DECL1(or, "orr %1, %0, %4", long, void, /* no return */ )
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ATOMIC_FUNC_DECL(inc_and_test, "add %1, %0, #1", long, long, ret==0 )
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ATOMIC_FUNC_DECL(dec_and_test, "sub %1, %0, #1", long, long, ret==0 )
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//ATOMIC_FUNC_DECL2(get_and_set, /* no extra op needed */ , long, long, ret)
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ATOMIC_XCHG_DECL(get_and_set, long)
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ATOMIC_CMPXCHG_DECL(cmpxchg, long)
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ATOMIC_FUNC_DECL1(add, "add %1, %0, %4", long, long, ret )
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#define atomic_inc(var) atomic_inc_int(&(var)->val)
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#define atomic_dec(var) atomic_dec_int(&(var)->val)
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#define atomic_and(var, mask) atomic_and_int(&(var)->val, (mask))
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#define atomic_or(var, mask) atomic_or_int(&(var)->val, (mask))
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#define atomic_dec_and_test(var) atomic_dec_and_test_int(&(var)->val)
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#define atomic_inc_and_test(var) atomic_inc_and_test_int(&(var)->val)
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#define atomic_get_and_set(var, i) atomic_get_and_set_int(&(var)->val, i)
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#define atomic_cmpxchg(var, old, new_v) \
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atomic_cmpxchg_int(&(var)->val, old, new_v)
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#define atomic_add(var, v) atomic_add_int(&(var)->val, (v))
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/* with integrated membar */
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#define mb_atomic_set_int(v, i) \
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do{ \
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membar(); \
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atomic_set_int(v, i); \
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}while(0)
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inline static int mb_atomic_get_int(volatile int* v)
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{
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membar();
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return atomic_get_int(v);
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}
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#define mb_atomic_inc_int(v) \
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do{ \
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membar(); \
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atomic_inc_int(v); \
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}while(0)
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#define mb_atomic_dec_int(v) \
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do{ \
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membar(); \
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atomic_dec_int(v); \
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}while(0)
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#define mb_atomic_or_int(v, m) \
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do{ \
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membar(); \
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atomic_or_int(v, m); \
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}while(0)
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#define mb_atomic_and_int(v, m) \
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do{ \
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membar(); \
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atomic_and_int(v, m); \
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}while(0)
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inline static int mb_atomic_inc_and_test_int(volatile int* v)
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{
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membar();
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return atomic_inc_and_test_int(v);
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}
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inline static int mb_atomic_dec_and_test_int(volatile int* v)
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{
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membar();
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return atomic_dec_and_test_int(v);
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}
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inline static int mb_atomic_get_and_set_int(volatile int* v, int i)
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{
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membar();
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return atomic_get_and_set_int(v, i);
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}
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inline static int mb_atomic_cmpxchg_int(volatile int* v, int o, int n)
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{
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membar();
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return atomic_cmpxchg_int(v, o, n);
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}
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inline static int mb_atomic_add_int(volatile int* v, int i)
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{
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membar();
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return atomic_add_int(v, i);
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}
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#define mb_atomic_set_long(v, i) \
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do{ \
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membar(); \
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atomic_set_long(v, i); \
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}while(0)
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inline static long mb_atomic_get_long(volatile long* v)
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{
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membar();
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return atomic_get_long(v);
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}
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#define mb_atomic_inc_long(v) \
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do{ \
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membar(); \
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atomic_inc_long(v); \
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}while(0)
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#define mb_atomic_dec_long(v) \
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do{ \
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membar(); \
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atomic_dec_long(v); \
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}while(0)
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#define mb_atomic_or_long(v, m) \
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do{ \
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membar(); \
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atomic_or_long(v, m); \
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}while(0)
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#define mb_atomic_and_long(v, m) \
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do{ \
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membar(); \
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atomic_and_long(v, m); \
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}while(0)
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inline static long mb_atomic_inc_and_test_long(volatile long* v)
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{
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membar();
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return atomic_inc_and_test_long(v);
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}
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inline static long mb_atomic_dec_and_test_long(volatile long* v)
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{
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membar();
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return atomic_dec_and_test_long(v);
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}
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inline static long mb_atomic_get_and_set_long(volatile long* v, long l)
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{
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membar();
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return atomic_get_and_set_long(v, l);
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}
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inline static long mb_atomic_cmpxchg_long(volatile long* v, long o, long n)
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{
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membar();
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return atomic_cmpxchg_long(v, o, n);
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}
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inline static long mb_atomic_add_long(volatile long* v, long i)
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{
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membar();
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return atomic_add_long(v, i);
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}
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#define mb_atomic_inc(var) mb_atomic_inc_int(&(var)->val)
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#define mb_atomic_dec(var) mb_atomic_dec_int(&(var)->val)
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#define mb_atomic_and(var, mask) mb_atomic_and_int(&(var)->val, (mask))
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#define mb_atomic_or(var, mask) mb_atomic_or_int(&(var)->val, (mask))
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#define mb_atomic_dec_and_test(var) mb_atomic_dec_and_test_int(&(var)->val)
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#define mb_atomic_inc_and_test(var) mb_atomic_inc_and_test_int(&(var)->val)
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#define mb_atomic_get(var) mb_atomic_get_int(&(var)->val)
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#define mb_atomic_set(var, i) mb_atomic_set_int(&(var)->val, i)
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#define mb_atomic_get_and_set(var, i) mb_atomic_get_and_set_int(&(var)->val, i)
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#define mb_atomic_cmpxchg(var, o, n) mb_atomic_cmpxchg_int(&(var)->val, o, n)
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#define mb_atomic_add(var, i) mb_atomic_add_int(&(var)->val, i)
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#else /* ! __CPU_arm6 => __CPU_arm */
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/* no atomic ops for v <6 , only SWP supported
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* Atomic ops could be implemented if one bit is sacrificed and used like
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* a spinlock, e.g:
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* mov %r0, #0x1
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* 1: swp %r1, %r0, [&atomic_val]
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* if (%r1 & 0x1) goto 1 # wait if first bit is 1
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* %r1>>=1 # restore the value (only 31 bits can be used )
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* %r1=op (%r1, ...)
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* %r1<<=1 # shift back the value, such that the first bit is 0
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* str %r1, [&atomic_val] # write the value
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*
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* However only 31 bits could be used (=> atomic_*_int and atomic_*_long
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* would still have to be lock based, since in these cases we guarantee all
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* the bits) and I'm not sure there would be a significant performance
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* benefit when compared with the fallback lock based version:
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* lock(atomic_lock);
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* atomic_val=op(*atomic_val, ...)
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* unlock(atomic_lock);
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*
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* -- andrei
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*/
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#endif /* __CPU_arm6 */
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#endif
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