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421 lines
12 KiB
421 lines
12 KiB
/*
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* Copyright (C) 2006 iptelorg GmbH
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* @file
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* @brief Atomic operations and memory barriers (MIPS isa 2 and MIPS64 specific)
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*
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* Atomic operations and memory barriers (MIPS isa 2 and MIPS64 specific)
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* \warning atomic ops do not include memory barriers, see atomic_ops.h for
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* more details.
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* \warning not tested on MIPS64 (not even a compile test)
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*
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* Config defines:
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* - NOSMP (in NOSMP mode it will also work on mips isa 1 CPUs that support
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* LL and SC, see MIPS_HAS_LLSC in atomic_ops.h)
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* - __CPU_MIPS64 (mips64 arch., in 64 bit mode: long and void* are 64 bits)
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* - __CPU_MIPS2 or __CPU_MIPS && MIPS_HAS_LLSC && NOSMP (if __CPU_MIPS64 is not defined)
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* @ingroup atomic
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*/
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/*
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* History:
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* --------
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* 2006-03-08 created by andrei
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* 2007-05-10 added atomic_add & atomic_cmpxchg (andrei)
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* 2007-05-29 added membar_depends(), membar_*_atomic_op and
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* membar_*_atomic_setget (andrei)
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*/
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#ifndef _atomic_mips2_h
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#define _atomic_mips2_h
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#define HAVE_ASM_INLINE_ATOMIC_OPS
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#define HAVE_ASM_INLINE_MEMBAR
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#ifdef __CPU_mips64
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#warning mips64 atomic code was not tested, please report problems to \
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serdev@iptel.org or andrei@iptel.org
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#endif
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#ifdef NOSMP
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#define membar() asm volatile ("" : : : "memory") /* gcc do not cache barrier*/
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#define membar_read() membar()
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#define membar_write() membar()
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#define membar_depends() do {} while(0) /* really empty, not even a cc bar. */
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/* lock barriers: empty, not needed for NOSMP; the lock/unlock should already
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* contain gcc barriers*/
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#define membar_enter_lock() do {} while(0)
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#define membar_leave_lock() do {} while(0)
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/* membars after or before atomic_ops or atomic_setget -> use these or
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* mb_<atomic_op_name>() if you need a memory barrier in one of these
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* situations (on some archs where the atomic operations imply memory
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* barriers is better to use atomic_op_x(); membar_atomic_op() then
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* atomic_op_x(); membar()) */
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#define membar_atomic_op() membar()
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#define membar_atomic_setget() membar()
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#define membar_write_atomic_op() membar_write()
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#define membar_write_atomic_setget() membar_write()
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#define membar_read_atomic_op() membar_read()
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#define membar_read_atomic_setget() membar_read()
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#else
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#define membar() \
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asm volatile( \
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".set push \n\t" \
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".set noreorder \n\t" \
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".set mips2 \n\t" \
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" sync\n\t" \
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".set pop \n\t" \
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: : : "memory" \
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)
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#define membar_read() membar()
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#define membar_write() membar()
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#define membar_depends() do {} while(0) /* really empty, not even a cc bar. */
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#define membar_enter_lock() membar()
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#define membar_leave_lock() membar()
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/* membars after or before atomic_ops or atomic_setget -> use these or
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* mb_<atomic_op_name>() if you need a memory barrier in one of these
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* situations (on some archs where the atomic operations imply memory
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* barriers is better to use atomic_op_x(); membar_atomic_op() then
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* atomic_op_x(); membar()) */
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#define membar_atomic_op() membar()
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#define membar_atomic_setget() membar()
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#define membar_write_atomic_op() membar_write()
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#define membar_write_atomic_setget() membar_write()
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#define membar_read_atomic_op() membar_read()
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#define membar_read_atomic_setget() membar_read()
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#endif /* NOSMP */
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/* main asm block */
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#define ATOMIC_ASM_OP_int(op) \
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".set push \n\t" \
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".set noreorder \n\t" \
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".set mips2 \n\t" \
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"1: ll %1, %0 \n\t" \
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" " op "\n\t" \
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" sc %2, %0 \n\t" \
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" beqz %2, 1b \n\t" \
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" nop \n\t" /* delay slot */ \
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".set pop \n\t"
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#ifdef __CPU_mips64
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#define ATOMIC_ASM_OP_long(op) \
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".set push \n\t" \
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".set noreorder \n\t" \
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"1: lld %1, %0 \n\t" \
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" " op "\n\t" \
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" scd %2, %0 \n\t" \
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" beqz %2, 1b \n\t" \
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" nop \n\t" /* delay slot */ \
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".set pop \n\t"
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#else /* ! __CPU_mips64 => __CPU_mips2 or __CPU_mips & MIPS_HAS_LLSC */
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#define ATOMIC_ASM_OP_long(op) ATOMIC_ASM_OP_int(op)
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#endif
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#define ATOMIC_FUNC_DECL(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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ATOMIC_ASM_OP_##P_TYPE(OP) \
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: "=m"(*var), "=&r"(ret), "=&r"(tmp) \
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: "m"(*var) \
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\
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); \
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return RET_EXPR; \
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}
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/* same as above, but with CT in %3 */
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#define ATOMIC_FUNC_DECL_CT(NAME, OP, CT, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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ATOMIC_ASM_OP_##P_TYPE(OP) \
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: "=m"(*var), "=&r"(ret), "=&r"(tmp) \
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: "r"((CT)), "m"(*var) \
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\
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); \
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return RET_EXPR; \
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}
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/* takes an extra param, i which goes in %3 */
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#define ATOMIC_FUNC_DECL1(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE i) \
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{ \
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P_TYPE ret, tmp; \
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asm volatile( \
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ATOMIC_ASM_OP_##P_TYPE(OP) \
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: "=m"(*var), "=&r"(ret), "=&r"(tmp) \
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: "r"((i)), "m"(*var) \
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\
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); \
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return RET_EXPR; \
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}
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/* takes an extra param, like above, but i goes in %2 */
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#define ATOMIC_FUNC_DECL2(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE i) \
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{ \
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P_TYPE ret; \
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asm volatile( \
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ATOMIC_ASM_OP_##P_TYPE(OP) \
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: "=m"(*var), "=&r"(ret), "+&r"(i) \
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: "m"(*var) \
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\
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); \
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return RET_EXPR; \
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}
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/* %0=var, %1=*var, %2=new, %3=old :
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* ret=*var; if *var==old then *var=new; return ret
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* => if succesfull (changed var to new) ret==old */
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#define ATOMIC_CMPXCHG_DECL(NAME, P_TYPE) \
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inline static P_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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P_TYPE old, \
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P_TYPE new_v) \
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{ \
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asm volatile( \
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ATOMIC_ASM_OP_##P_TYPE("bne %1, %3, 2f \n\t nop") \
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"2: \n\t" \
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: "=m"(*var), "=&r"(old), "=r"(new_v) \
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: "r"(old), "m"(*var), "2"(new_v) \
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\
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); \
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return old; \
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}
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ATOMIC_FUNC_DECL(inc, "addiu %2, %1, 1", int, void, /* no return */ )
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ATOMIC_FUNC_DECL_CT(dec, "subu %2, %1, %3", 1, int, void, /* no return */ )
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ATOMIC_FUNC_DECL1(and, "and %2, %1, %3", int, void, /* no return */ )
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ATOMIC_FUNC_DECL1(or, "or %2, %1, %3", int, void, /* no return */ )
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ATOMIC_FUNC_DECL(inc_and_test, "addiu %2, %1, 1", int, int, (ret+1)==0 )
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ATOMIC_FUNC_DECL_CT(dec_and_test, "subu %2, %1, %3", 1, int, int, (ret-1)==0 )
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ATOMIC_FUNC_DECL2(get_and_set, "" /* nothing needed */, int, int, ret )
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ATOMIC_CMPXCHG_DECL(cmpxchg, int)
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ATOMIC_FUNC_DECL1(add, "addu %2, %1, %3 \n\t move %1, %2", int, int, ret )
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#ifdef __CPU_mips64
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ATOMIC_FUNC_DECL(inc, "daddiu %2, %1, 1", long, void, /* no return */ )
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ATOMIC_FUNC_DECL_CT(dec, "dsubu %2, %1, %3", 1, long, void, /* no return */ )
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ATOMIC_FUNC_DECL1(and, "and %2, %1, %3", long, void, /* no return */ )
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ATOMIC_FUNC_DECL1(or, "or %2, %1, %3", long, void, /* no return */ )
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ATOMIC_FUNC_DECL(inc_and_test, "daddiu %2, %1, 1", long, long, (ret+1)==0 )
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ATOMIC_FUNC_DECL_CT(dec_and_test, "dsubu %2, %1, %3", 1,long, long, (ret-1)==0 )
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ATOMIC_FUNC_DECL2(get_and_set, "" /* nothing needed */, long, long, ret )
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ATOMIC_CMPXCHG_DECL(cmpxchg, long)
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ATOMIC_FUNC_DECL1(add, "daddu %2, %1, %3 \n\t move %1, %2", long, long, ret )
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#else /* ! __CPU_mips64 => __CPU_mips2 or __CPU_mips */
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ATOMIC_FUNC_DECL(inc, "addiu %2, %1, 1", long, void, /* no return */ )
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ATOMIC_FUNC_DECL_CT(dec, "subu %2, %1, %3", 1, long, void, /* no return */ )
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ATOMIC_FUNC_DECL1(and, "and %2, %1, %3", long, void, /* no return */ )
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ATOMIC_FUNC_DECL1(or, "or %2, %1, %3", long, void, /* no return */ )
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ATOMIC_FUNC_DECL(inc_and_test, "addiu %2, %1, 1", long, long, (ret+1)==0 )
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ATOMIC_FUNC_DECL_CT(dec_and_test, "subu %2, %1, %3", 1,long, long, (ret-1)==0 )
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ATOMIC_FUNC_DECL2(get_and_set, "" /* nothing needed */, long, long, ret )
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ATOMIC_CMPXCHG_DECL(cmpxchg, long)
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ATOMIC_FUNC_DECL1(add, "addu %2, %1, %3 \n\t move %1, %2", long, long, ret )
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#endif /* __CPU_mips64 */
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#define atomic_inc(var) atomic_inc_int(&(var)->val)
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#define atomic_dec(var) atomic_dec_int(&(var)->val)
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#define atomic_and(var, mask) atomic_and_int(&(var)->val, (mask))
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#define atomic_or(var, mask) atomic_or_int(&(var)->val, (mask))
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#define atomic_dec_and_test(var) atomic_dec_and_test_int(&(var)->val)
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#define atomic_inc_and_test(var) atomic_inc_and_test_int(&(var)->val)
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#define atomic_get_and_set(var, i) atomic_get_and_set_int(&(var)->val, i)
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#define atomic_add(var, i) atomic_add_int(&(var)->val, i)
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#define atomic_cmpxchg(var, old, new_v) \
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atomic_cmpxchg_int(&(var)->val, old, new_v)
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/* with integrated membar */
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#define mb_atomic_set_int(v, i) \
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do{ \
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membar(); \
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atomic_set_int(v, i); \
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}while(0)
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inline static int mb_atomic_get_int(volatile int* v)
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{
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membar();
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return atomic_get_int(v);
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}
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#define mb_atomic_inc_int(v) \
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do{ \
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membar(); \
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atomic_inc_int(v); \
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}while(0)
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#define mb_atomic_dec_int(v) \
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do{ \
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membar(); \
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atomic_dec_int(v); \
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}while(0)
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#define mb_atomic_or_int(v, m) \
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do{ \
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membar(); \
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atomic_or_int(v, m); \
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}while(0)
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#define mb_atomic_and_int(v, m) \
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do{ \
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membar(); \
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atomic_and_int(v, m); \
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}while(0)
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inline static int mb_atomic_inc_and_test_int(volatile int* v)
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{
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membar();
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return atomic_inc_and_test_int(v);
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}
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inline static int mb_atomic_dec_and_test_int(volatile int* v)
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{
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membar();
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return atomic_dec_and_test_int(v);
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}
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inline static int mb_atomic_get_and_set_int(volatile int* v, int i)
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{
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membar();
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return atomic_get_and_set_int(v, i);
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}
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inline static int mb_atomic_cmpxchg_int(volatile int* v, int o, int n)
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{
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membar();
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return atomic_cmpxchg_int(v, o, n);
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}
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inline static int mb_atomic_add_int(volatile int* v, int i)
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{
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membar();
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return atomic_add_int(v, i);
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}
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#define mb_atomic_set_long(v, i) \
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do{ \
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membar(); \
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atomic_set_long(v, i); \
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}while(0)
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inline static long mb_atomic_get_long(volatile long* v)
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{
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membar();
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return atomic_get_long(v);
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}
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#define mb_atomic_inc_long(v) \
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do{ \
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membar(); \
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atomic_inc_long(v); \
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}while(0)
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#define mb_atomic_dec_long(v) \
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do{ \
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membar(); \
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atomic_dec_long(v); \
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}while(0)
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#define mb_atomic_or_long(v, m) \
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do{ \
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membar(); \
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atomic_or_long(v, m); \
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}while(0)
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#define mb_atomic_and_long(v, m) \
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do{ \
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membar(); \
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atomic_and_long(v, m); \
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}while(0)
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inline static long mb_atomic_inc_and_test_long(volatile long* v)
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{
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membar();
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return atomic_inc_and_test_long(v);
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}
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inline static long mb_atomic_dec_and_test_long(volatile long* v)
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{
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membar();
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return atomic_dec_and_test_long(v);
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}
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inline static long mb_atomic_get_and_set_long(volatile long* v, long l)
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{
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membar();
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return atomic_get_and_set_long(v, l);
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}
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inline static long mb_atomic_cmpxchg_long(volatile long* v, long o, long n)
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{
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membar();
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return atomic_cmpxchg_long(v, o, n);
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}
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inline static long mb_atomic_add_long(volatile long* v, long i)
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{
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membar();
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return atomic_add_long(v, i);
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}
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#define mb_atomic_inc(var) mb_atomic_inc_int(&(var)->val)
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#define mb_atomic_dec(var) mb_atomic_dec_int(&(var)->val)
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#define mb_atomic_and(var, mask) mb_atomic_and_int(&(var)->val, (mask))
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#define mb_atomic_or(var, mask) mb_atomic_or_int(&(var)->val, (mask))
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#define mb_atomic_dec_and_test(var) mb_atomic_dec_and_test_int(&(var)->val)
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#define mb_atomic_inc_and_test(var) mb_atomic_inc_and_test_int(&(var)->val)
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#define mb_atomic_get(var) mb_atomic_get_int(&(var)->val)
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#define mb_atomic_set(var, i) mb_atomic_set_int(&(var)->val, i)
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#define mb_atomic_get_and_set(var, i) mb_atomic_get_and_set_int(&(var)->val, i)
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#define mb_atomic_cmpxchg(var, o, n) mb_atomic_cmpxchg_int(&(var)->val, o, n)
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#define mb_atomic_add(var, i) mb_atomic_add_int(&(var)->val, i)
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#endif
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