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186 lines
8.9 KiB
186 lines
8.9 KiB
/*
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* $Id$
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*
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* Copyright (C) 2006 iptelorg GmbH
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*!
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* \file
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* \brief SIP-router core :: Atomic operations and memory barriers
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* \ingroup core
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* Module: \ref core
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* See \ref atomic
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*/
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/*
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* \page atomicops Atomic operations and memory barriers
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*
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* WARNING: atomic ops do not include memory barriers
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*
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* memory barriers:
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* ----------------
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*
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* void membar(); - memory barrier (load & store)
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* void membar_read() - load (read) memory barrier
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* void membar_write() - store (write) memory barrier
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* void membar_depends() - read depends memory barrier, needed before using
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* the contents of a pointer (for now is needed only
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* on Alpha so on all other CPUs it will be a no-op)
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* For more info see:
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* http://lse.sourceforge.net/locking/wmbdd.html
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* http://www.linuxjournal.com/article/8212
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*
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* void membar_enter_lock() - memory barrier function that should be
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* called after a lock operation (where lock is
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* an asm inline function that uses atomic store
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* operation on the lock var.). It is at most
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* a StoreStore|StoreLoad barrier, but could also
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* be empty if an atomic op implies a memory
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* barrier on the specific arhitecture.
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* Example usage:
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* raw_lock(l); membar_enter_lock(); ...
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* void membar_leave_lock() - memory barrier function that should be called
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* before an unlock operation (where unlock is an
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* asm inline function that uses at least an atomic
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* store to on the lock var.). It is at most a
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* LoadStore|StoreStore barrier (but could also be
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* empty, see above).
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* Example: raw_lock(l); membar_enter_lock(); ..
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* ... critical section ...
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* membar_leave_lock(); raw_unlock(l);
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* void membar_atomic_op() - memory barrier that should be called if a memory
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* barrier is needed immediately after or
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* immediately before an atomic operation
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* (for example: atomic_inc(&i); membar_atomic_op()
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* instead of atomic_inc(&i); membar()).
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* atomic_op means every atomic operation except get
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* and set (for them use membar_atomic_setget()).
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* Using membar_atomic_op() instead of membar() in
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* these cases will generate faster code on some
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* architectures (for now x86 and x86_64), where
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* atomic operations act also as memory barriers.
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* Note that mb_atomic_<OP>(...) is equivalent to
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* membar_atomic_op(); atomic_<OP>(...) and in this
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* case the first form is preferred).
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* void membar_atomic_setget() - same as above but for atomic_set and
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* atomic_get (and not for any other atomic op.,
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* including atomic_get_and_set, for them use
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* membar_atomic_op()).
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* Note that mb_atomic_{get,set}(&i) is equivalent
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* and preferred to membar_atomic_setget();
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* atomic_{get,set}(&i) (it will generate faster
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* code on x86 and x86_64).
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* void membar_read_atomic_op() - like membar_atomic_op(), but acts only as
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* a read barrier.
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* void membar_read_atomic_setget() - like membar_atomic_setget() but acts only
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* as a read barrier.
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* void membar_write_atomic_op() - like membar_atomic_op(), but acts only as
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* a write barrier.
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* void membar_write_atomic_setget() - like membar_atomic_setget() but acts
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* only as a write barrier.
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*
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*
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* Note: - properly using memory barriers is tricky, in general try not to
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* depend on them. Locks include memory barriers, so you don't need
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* them for writes/load already protected by locks.
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* - membar_enter_lock() and membar_leave_lock() are needed only if
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* you implement your own locks using atomic ops (ser locks have the
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* membars included)
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*
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* atomic operations:
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* ------------------
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* type: atomic_t
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*
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* not including memory barriers:
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*
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* void atomic_set(atomic_t* v, int i) - v->val=i
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* int atomic_get(atomic_t* v) - return v->val
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* int atomic_get_and_set(atomic_t *v, i) - return old v->val, v->val=i
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* void atomic_inc(atomic_t* v)
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* void atomic_dec(atomic_t* v)
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* int atomic_inc_and_test(atomic_t* v) - returns 1 if the result is 0
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* int atomic_dec_and_test(atomic_t* v) - returns 1 if the result is 0
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* void atomic_or (atomic_t* v, int mask) - v->val|=mask
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* void atomic_and(atomic_t* v, int mask) - v->val&=mask
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* int atomic_add(atomic_t* v, int i) - v->val+=i; return v->val
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* int atomic_cmpxchg(atomic_t* v, o, n) - r=v->val; if (r==o) v->val=n;
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* return r (old value)
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*
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*
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* same ops, but with builtin memory barriers:
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*
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* void mb_atomic_set(atomic_t* v, int i) - v->val=i
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* int mb_atomic_get(atomic_t* v) - return v->val
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* int mb_atomic_get_and_set(atomic_t *v, i) - return old v->val, v->val=i
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* void mb_atomic_inc(atomic_t* v)
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* void mb_atomic_dec(atomic_t* v)
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* int mb_atomic_inc_and_test(atomic_t* v) - returns 1 if the result is 0
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* int mb_atomic_dec_and_test(atomic_t* v) - returns 1 if the result is 0
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* void mb_atomic_or(atomic_t* v, int mask - v->val|=mask
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* void mb_atomic_and(atomic_t* v, int mask)- v->val&=mask
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* int mb_atomic_add(atomic_t* v, int i) - v->val+=i; return v->val
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* int mb_atomic_cmpxchg(atomic_t* v, o, n) - r=v->val; if (r==o) v->val=n;
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* return r (old value)
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*
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* Same operations are available for int and long. The functions are named
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* after the following rules:
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* - add an int or long suffix to the correspondent atomic function
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* - volatile int* or volatile long* replace atomic_t* in the functions
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* declarations
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* - long and int replace the parameter type (if the function has an extra
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* parameter) and the return value
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* E.g.:
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* long atomic_get_long(volatile long* v)
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* int atomic_get_int( volatile int* v)
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* long atomic_get_and_set(volatile long* v, long l)
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* int atomic_get_and_set(volatile int* v, int i)
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*
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* Config defines: CC_GCC_LIKE_ASM - the compiler support gcc style
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* inline asm
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* NOSMP - the code will be a little faster, but not SMP
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* safe
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* __CPU_i386, __CPU_x86_64, X86_OOSTORE - see
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* atomic/atomic_x86.h
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* __CPU_mips, __CPU_mips2, __CPU_mips64, MIPS_HAS_LLSC - see
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* atomic/atomic_mip2.h
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* __CPU_ppc, __CPU_ppc64 - see atomic/atomic_ppc.h
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* __CPU_sparc - see atomic/atomic_sparc.h
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* __CPU_sparc64, SPARC64_MODE - see atomic/atomic_sparc64.h
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* __CPU_arm, __CPU_arm6 - see atomic/atomic_arm.h
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* __CPU_alpha - see atomic/atomic_alpha.h
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*/
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/*
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* History:
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* --------
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* 2006-03-08 created by andrei
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* 2007-05-13 moved some of the decl. and includes into atomic_common.h and
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* atomic_native.h (andrei)
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*/
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#ifndef __atomic_ops
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#define __atomic_ops
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#include "atomic/atomic_common.h"
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#include "atomic/atomic_native.h"
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/*! \brief if no native operations, emulate them using locks */
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#if ! defined HAVE_ASM_INLINE_ATOMIC_OPS || ! defined HAVE_ASM_INLINE_MEMBAR
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#include "atomic/atomic_unknown.h"
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#endif /* if HAVE_ASM_INLINE_ATOMIC_OPS */
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#endif
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